
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 131
PIC18C601/801
11.1
Timer1 Operation
Timer1 can operate in one of these modes:
As a timer
As a synchronous counter
As an asynchronous counter
The operating mode is determined by the clock select
bit, TMR1CS (T1CON register).
When TMR1CS is clear, Timer1 increments every
instruction cycle. When TMR1CS is set, Timer1 incre-
ments on every rising edge of the external clock input
or the Timer1 oscillator, if enabled.
When the Timer1 oscillator is enabled (T1OSCEN is set),
the RC1/T1OSI and RC0/T1OSO/T1CKI pins become
inputs. That is, the TRISC<1:0> value is ignored.
Timer1 also has an internal “RESET input”. This RESET
FIGURE 11-1:
TIMER1 BLOCK DIAGRAM
Note:
When Timer1 is configured in an Asyn-
chronous mode, care must be taken to
make sure that there is no incoming pulse
while Timer1 is being turned off. If there is
an incoming pulse while Timer1 is being
turned off, Timer1 value may become
unpredictable.
If an application requires that Timer1 be
turned off and if it is possible that Timer1
may receive an incoming pulse while being
turned off, synchronize the external clock
first, by clearing the T1SYNC bit of register
T1CON. Please note that this may cause
Timer1 to miss up to one count.
TMR1H
TMR1L
T1SYNC
TMR1CS
T1CKPS1:T1CKPS0
SLEEP Input
FOSC/4
Internal
Clock
TMR1ON
On/Off
Prescaler
1, 2, 4, 8
Synchronize
det
1
0
1
Synchronized
Clock Input
2
TMR1IF
Overflow
TMR1
CLR
CCP Special Event Trigger
T1OSCEN
Enable
Oscillator(1)
T1OSC
Interrupt
Flag Bit
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This reduces power drain.
T1OSI
T13CKI/T1OSO